Chip
Chip, also known as microcircuit, microchip, or integrated circuit (English: integrated circuit, IC). It is a silicon chip containing an integrated circuit, which is very small and often part of a computer or other electronic device.
Chip, English for Chip; chipset for Chipset. chip generally refers to the carrier of the integrated circuit, but also the integrated circuit after design, manufacturing, packaging, testing, usually an independent whole that can be used immediately. The two words "chip" and "integrated circuit" are often used together, for example, in the usual discussion topics, integrated circuit design and chip design is said to mean one thing, chip industry, integrated circuit industry, IC industry, IC industry is often a meaning. In fact, these two terms have a connection and a difference. Integrated circuit entities often have to exist in the form of chips, because the narrow sense of integrated circuit, is to emphasize the circuit itself, for example, as simple as only five components connected together to form a phase shift oscillator, when it is still presented on the drawing, we can also call it an integrated circuit, when we want to take this small integrated circuit to apply, then it must be a separate piece of physical, or embedded in a larger integrated circuit When we want to take this small integrated circuit to apply, then it must be a separate piece of physical, or embedded in a larger integrated circuit, relying on the chip to play his role; integrated circuit more emphasis on the design and layout of the circuit wiring, the chip more emphasis on circuit integration, production and packaging. And the broad sense of integrated circuit, when it comes to the industry (distinguished from other industries), can also include a variety of chip-related meanings.
The chip also has its unique place. Broadly speaking, any semiconductor chip manufactured using microfabrication means can be called a chip, and does not necessarily have a circuit inside. Examples include semiconductor light source chips; mechanical chips, such as MEMS gyroscopes; or biological chips such as DNA chips. In communication and information technology, when limited to silicon integrated circuits, the intersection of a chip and an integrated circuit is the "circuit on a silicon wafer". Chipset, on the other hand, is a series of interrelated chip combinations, which are interdependent and can play a greater role when combined together, such as the processor and north-south bridge chipset inside a computer, and the RF, baseband and power management chipset inside a cell phone.
Chip design flow
Chip design is divided into front-end design and back-end design, front-end design (also known as logic design) and back-end design (also known as physical design) is not unified and strict boundaries, involving the design related to the process is the back-end design.
Chip design front-end design
1. Specification development
Chip specification, also like a feature list, is a design requirement that the customer puts forward to the chip design company (called Fabless, waferless design company), including the specific functional and performance requirements that the chip needs to achieve.
2. Detailed design
Fabless comes up with a design solution and a specific implementation architecture that divides the module functionality based on the specifications proposed by the customer.
3. HDL Coding
The module functions are described in code using hardware description languages (VHDL, Verilog HDL, the latter is generally used by industry companies), i.e. the actual hardware circuit functions are described in HDL to form RTL (Register Transfer Level) code.
4. Simulation verification
Simulation verification is to check the correctness of the coded design, and the criterion for this is the specification developed in the first step. The test is whether the design accurately meets all the requirements of the specification. The specification is the gold standard for the correctness of the design, and all violations, which do not meet the specification requirements, require reworking the design and coding. Design and simulation verification is an iterative process until the verification results show full compliance with the specification criteria.
Simulation and verification tools Synopsys' VCS, and Cadence's NC-Verilog.
5. Logic synthesis - Design Compiler
The simulation is verified and logic synthesis is performed. Logic synthesis results in the translation of the HDL code implemented in the design into a gate-level netlist. synthesis requires a set of constraints, which are the criteria you want the synthesized circuit to meet in terms of area, timing, and other target parameters. Logic synthesis is based on a specific synthesis library, and the area and timing parameters of the basic standard cell of a gate circuit are different from one library to another. Therefore, the selected synthesis library is not the same, the synthesized circuit in the timing, and area is different. Generally speaking, after the synthesis is completed, the simulation needs to be done again to verify (this is also called post-simulation, and the previous one is called pre-simulation).
Logic synthesis tool Synopsys' Design Compiler.
6. STA
Static Timing Analysis (STA), static timing analysis, which also belongs to the verification category, it is mainly in the timing of the circuit to verify whether the circuit exists to establish the time (setup time) and hold time (hold time) violation (violation). This is a digital circuit basics, a register with these two timing violations, there is no way to correctly sample data and output data, so the digital chip function based on the register will definitely have problems.
STA tools are Synopsys' Prime Time.
7. Formal verification
This is also the verification category, which is the verification of the synthesized netlist from the function (STA is timing). A common method is the equivalence check, where the HDL design after functional verification is used as a reference to compare the synthesized netlist functions and whether they are functionally equivalent. This is done to ensure that the circuit functions described in the original HDL were not changed during the logic synthesis.
Formality verification tools are available from Synopsys' Formality.
The flow of the front-end design is written here for now. In terms of the extent of the design, the front-end design results in a gate-level netlist circuit for the chip.
Chip design back-end design
1. DFT
Design For Test (DFT) is a design for testability. A common method of DFT is to insert a scan chain into the design to turn non-scan cells (such as registers) into scan cells. About DFT, some books have detailed descriptions, but compared to the picture will be better to understand a little.
DFT tool Synopsys DFT Compiler
2. Layout planning (FloorPlan)
Layout planning is the placement of the chip's macro cell module, in general to determine the placement of various functional circuits, such as IP modules, RAM, I/O pins, etc.. Layout planning can directly affect the final area of the chip.
The tool is Synopsys' Astro
3. CTS
Clock Tree Synthesis, simply put, is the wiring of the clock. Due to the global command role of the clock signal in the digital chip, its distribution should be symmetrically connected to each register cell so that the clock arrives at each register from the same clock source with minimal difference in clock delay. This is why the clock signal needs to be wired separately.
CTS tool, Synopsys' Physical Compiler
4. Place & Route
Here the wiring is the general signal wiring, including the alignment between various standard units (basic logic gate circuits). For example, we usually hear the 0.13um process, or 90nm process, is actually the minimum width that can be achieved here metal wiring, from a microscopic point of view is the MOS tube channel length.
The tool Synopsys' Astro
5. parasitic parameter extraction
Due to the resistance of the wire itself, the mutual inductance between adjacent wires, coupling capacitance inside the chip will generate signal noise, crosstalk and reflection. These effects can create signal integrity problems, resulting in signal voltage fluctuations and variations, and if severe, can lead to signal distortion errors. It is very important to extract parasitic parameters for re-analysis and verification to analyze signal integrity issues.
Tools Synopsys' Star-RCXT
6. Physical verification of the layout
The physical layout of the completed wiring for functional and timing verification, verification items, such as LVS (Layout Vs Schematic) verification, simply put, is the layout and logic synthesis of the gate level circuit diagram comparison verification; DRC (Design Rule Checking): design rule check, check the wire spacing, wire width, etc. to meet the process requirements, ERC (Electrical Rule Checking) (Electrical Rule Checking): electrical rule checking, checking short circuit and open circuit and other electrical rule violations; and so on.
The tool is Hercules from Synopsys
The actual back-end process also includes circuit power analysis, as well as DFM (Design for Manufacturability) issues that arise as manufacturing processes continue to advance, which are not addressed here.
The completion of physical layout verification is the completion of the entire chip design phase, and the following is the chip manufacturing. The physical layout is given to the chip foundry (called Foundry) in GDS II file format to make the actual circuit on the silicon wafer, and then package and test it to get the actual chip we see.
Chip design process files
In the chip design important design aspects, such as comprehensive and timing analysis, layout drawing, etc. need to use the process library file, and we often lack knowledge of the process file, so it is difficult to learn some of the chip design things on their own. For example, there is no process library files, learning layout design is a paper exercise. This article focuses on process library-related knowledge.
Process files are provided by chip makers, so a general understanding of what chip makers are available domestically and internationally is necessary. Internationally, there are major semiconductor manufacturers such as TSMC, Intel, and Samsung. Domestically, there are mainly companies such as SMIC, China Resources ShangHua, Shenzhen Founder, etc. These companies provide relevant process library documents, but only if they cooperate with these companies to obtain them, and these process documents are confidential.
The main components of the complete process library files are
1, simulation simulation process library, mainly to support spectre and hspice this two software, the suffix name is scs - spectre use, lib - hspice use.
2, analog layout library files, mainly for cadence layout drawing software, suffix name tf,drf.
3, digital synthesis library, mainly contains the timing library, the basic netlist components and other related synthesis and timing analysis of the library files needed. It is mainly used for DC software synthesis and PT software timing analysis.
4, digital layout library, mainly for cadence encounter software for automatic layout wiring, of course, automatic layout wiring tools will also use the timing library, comprehensive constraint files, etc.
5, layout verification library, mainly DRC, LVS check. Some are specifically to support calibre, some specifically to support dracula, diva and other layout checking tools. Each library file has the corresponding pdf description of the document.
Reverse design will use 1, 2, 5 and other process library files, 3 and 4 will not be used. Forward design (forward design from the code) is required to use all the files. Because the process file in the chip design occupies an extremely important position, in each key design aspects to be used, coupled with its confidential properties, so the network is difficult to find the complete process file for personal learning, EETOP on a cadence public for personal learning process library file can facilitate learning, but also seems to be incomplete.
Synthesis of Chip Design
What is synthesis? Synthesis is the process of converting/mapping RTL-level verilog code into a circuit represented by a base gate cell using the Design Compiler tool. The basic gate-level cell is what we usually learn with and without gate, or non-gate, register and so on, but, these gate-level cells have been made into a standard cell library, we can directly use the software to call, rather than need to call their own gate-level cells to build the circuit. In short, Design Compiler software is to do the translation work - the translation of the code into the actual circuit, but not just translation so simple, it involves the optimization of the circuit and timing constraints, so that it meets the performance requirements we do develop. As mentioned earlier, the software is constraint-driven, so where do the constraints come from? The answer is, the design specification. Each chip design project will have a project specification, which is to be developed at the beginning of the chip design, the overall planning (see previous article) steps. Specific detailed constraints require careful discretionary decisions during the synthesis process. The general flow of synthesis.
1, the pre-synthesis process.
2, the process of imposing design constraints.
3, the design synthesis process.
4, post-integration process.
PS, a necessary condition for using Design Compiler software is to learn to use DC TCL scripts.
Pre-synthesis process. This part is mainly to prepare the library files used in the synthesis process (including process libraries, link libraries, symbol libraries, synthesis libraries), design input files, and set up the environment parameters.
Applying design constraints process. This part is mainly to prepare the constraint files with DC TCL scripts. The specific constraint items can be divided into three main categories.
a,area constraints, defining clocks, constraining input/output paths.
b (environmental attributes), constraint input driver, constraint output load, set operating conditions (best, typical, worst case), set connected load model.
c (advanced clock constraints), the clock jitter, offset, clock source delay, synchronous multi-clock, asynchronous clock, multi-cycle path, these types of detailed constraints.
That's all there is to the constraints specifically. A detailed TCL script constraint file basically contains all of the above constraints. A sample constraint file follows.
Design synthesis process. It mainly introduces the circuit module design planning (for better constraints), the Design Compiler synthesis optimization process (three major optimization stages, structure level, logic level, and gate level), the specific process of timing analysis, and some other details of the synthesis process.
After the synthesis process. How to see the results after synthesis and how to solve timing violations? This is the problem that the post-synthesis process is designed to solve. After synthesis, by analyzing the synthesis report, you can know how the circuit synthesis result is, and according to the non-conforming requirements, you can restrain or even redesign the circuit. At this stage, it is particularly worth mentioning the synthesis pre-estimation, because when writing the synthesis constraint script, it is necessary to determine the constraints, and specifications are generally not able to cover such a detailed part, so it is necessary to carry out a synthesis pre-estimation based on the actual circuit, this step is done at the same time as the verification after the code is written, in order to roughly estimate whether the circuit meets the requirements, at this time the pre-synthesis process is the same as the formal The pre-synthesis process is the same as the formal synthesis, but the requirements are much more lenient, with a timing violation requirement of about 10%-15%, which means that it does not matter if 10%-15% of the circuit does not meet the timing.
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